This invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to a novel and improved decoupling capacitor, and method of formation thereof wherein the capacitors are formed from a pair of lead frames disposed in a parallel orientation and including multi-layer ceramic capacitor chips having top and bottom electrodes. This dual lead frame construction and specially configured multi-layer capacitor chip permits the decoupling capacitor to be formed from a lamination process without the use of any molding to form decoupling capacitors which are auto-insertable into printed circuit boards for use in conjunction with dual-in-line integrated circuits or other electronic components.
U.S. Pat. No. 4,502,101 (which is assigned to the assignee hereof, and the entire contents of which are incorporated herein by reference) discloses a decoupling capacitor for an integrated circuit package. The decoupling capacitor of that prior patent is a thin rectangular chip of ceramic material which is metallized on opposite sides and has leads from the metallized coatings on opposite sides of the chip at two points adjacent a pair of diagonally opposed corners of the rectangularly shaped ceramic chip. The two leads are bend downwardly, and the decoupling capacitor assembly is encapsulated in a film of nonconductive material. In accordance with the teachings of that prior application, the decoupling capacitor is dimensioned so as to be received in the space between the two rows of leads extending from a conventional dual-in-line integrated circuit. The two leads from the decoupling capacitor are plugged into a printed circuit board, with these leads from the capacitor being inserted into the printed circuit through holes to which the ground and power supply conductors are connected. The associated integrated circuit or other electronic component is then positioned over the capacitor and inserted into the board such that the power supply leads of the integrated circuit or other component will be positioned in the same through holes of the printed circuit board in which the two capacitor leads have been inserted.
The diagonally located leads or pins on the decoupling capacitor of U.S. Pat. No. 4,502,101 have resulted in a problem when it is desired to automatically insert the decoupling capacitors into the printed circuit board. Standard auto-insertion equipment is available for inserting integrated circuit elements into the printed circuit boards. The insertion heads on standard auto-insertion equipment grasp the integrated circuit about the bent terminal pins or leads of the integrated circuit. Since there are two symmetric rows of pins on the integrated circuit element, the auto-insertion equipment can grasp the integrated circuit element symmetrically and stably for insertion. However, when insertion of the decoupling capacitor of prior U.S. Pat. No. 4,502,101 is attempted with the same auto-insertion equipment, an unstable condition and misalignment results because of the fact that the decoupling capacitor, rather than having two symmetrical rows of pins, has only two pins at diagonally opposite corners of the rectangular capacitor. Because of the presence of only the two pins, the capacitor "cocks" in the insertion head with the result that misalignment occurs between the terminals of the capacitor in the corresponding holes on the printed circuit board.
Since it is extremely desirable to auto-insert the decoupling capacitors into the printed circuit boards, and since it is equally desirable to perform that auto-insertion with the same auto-insertion equipment used with the integrated circuit elements, a significant problem is encountered with the decoupling capacitor of the prior application, not from the standpoint of its electronic operability and effectiveness, but rather from the standpoint of adapting it to high volume assembly techniques.
A need also exists for a decoupling capacitor structure which is also auto-insertable, hermetically sealed, and capable of being manufactured by automated assembly processes.
U.S. Pat. No. 4,475,143 (assigned to the assignee hereof) discloses one approach to solving the above discussed auto-insertion problem by the incorporation of dummy or stabilizing pins in a decoupling capacitor assembly. U.S. Pat. Nos. 4,491,895, 4,494,169, 4,494,170, 4,497,012, 4,511,951, 4,532,572, and U.S. patent application Ser. No. 711,393 to Kask, Hernandez and Watson filed on Mar. 13, 1985, now U.S. Pat. No. 4,630,170 issued Dec. 16, 1986, all of which are assigned to the assignee hereof, present other constructions of and methods for forming decoupling capacitors with dummy pins or molded stabilizing lugs.
Presently used manufacturing procedures for decoupling capacitors of the type hereinabove discussed (i.e., which include dummy leads) are not particularly well suited for incorporating multi-layer monolithic ceramic capacitor chips as the capacitive element for the decoupling capacitor device. In effect then, this situation limits the capacitive element to be a single layer capacitor of limited obtainable capacitance per unit volume. However, a method of manufacturing decoupling capacitors with multi-layer ceramic capacitor chips with only two leads (i.e., no dummy leads) is disclosed in U.S. patent application Ser. No. 690,117, now U.S. Pat. No. 4,584,627, which is assigned to the assignee hereof and incorporated herein by reference. An alternative method of manufacturing a decoupling capacitor having four leads and with multi-layer ceramic chips is disclosed in U.S. patent application Ser. No. 711,478 to Schilling, Jodoin and Johnston filed on Mar. 13, 1985 now U.S. Pat. No. 4,622,619.
Many of these prior art methods of manufacturing decoupling capacitors utilize encapsulating molding as a technique in providing hermetically sealed components. One of the problems associated with conventional multi-layer ceramic capacitors using either transfer or injection molding, is the resultant relatively small total package thickness of about 0.045 inch (including stand-offs). This leads to a package wall thickness of about 0.008-0.010 inch, which is quite difficult to consistently provide using conventional state of the art molding methods.
It should be understood that there is a need for efficient and economical decoupling capacitors and methods of manufacture thereof having higher capacitance volumes for use in decoupling the new generation of integrated circuit devices, which are faster and consume more power (i.e., 256K memory integrated circuits). One attempt at overcoming some of the above-discussed problems is disclosed in co-pending U.S. patent application Ser. No. 730,278, filed May 3, 1985 now U.S. Pat. No. 4,594,641.